1. Field of the Invention
The present invention refers to a method for writing data into a memory cell of a conductive bridging random access memory and to a memory circuit comprising memory cells with programmable metallization cells, particularly a CBRAM memory circuit.
2. Description of the Related Art
Memory cells comprising a solid electrolyte material are well known as PMC (programmable metallization cell) memory cells. Memory devices including such PMC memory cells are known as CBRAM (conductive-bridging random access memory) devices. The storing of different states in a PMC memory cell is based on the developing or diminishing of a conductive path in the electrolyte material between electrodes based on an applied electrical field. Although the electrolyte material has a high resistance, the conductive path between electrodes has a low resistance. Thereby, the PMC memory cell can be set to different states depending on the resistance of the PMC memory element. Usually, both states of the PMC memory cell are sufficiently time-stable in such a way that data may permanently be stored.
A PMC memory cell is operated by applying a positive or a negative voltage to the solid electrolyte of the PMC memory element. In order to store data into the PMC memory cell, the PMC memory cell is brought to a programmed stated by applying a suitable programming voltage to the PMC memory cell which results in the development of the conductive path in the electrolyte material and therefore in the setting of a first state with low resistance. In order to store a second state in the PMC memory cell with high resistance, an erase voltage has to be supplied in such a manner that the resistance of the PMC memory cell changes back to a high resistance which refers to an erased state. To read out a PMC memory cell, a read voltage is applied that is lower than the programming voltage. With the read voltage, a current through the resistance of the PMC memory element is detected and associated to the respective low or high resistance state of the PMC memory cell.
U.S. Pat. No. 6,865,117 B2 describes a programming circuit for a programmable microelectronic device, a system including the circuit and a method for forming the same. The circuit is configured to provide a reversible bias across the microelectronic device to perform erase and write functions. One configuration of the programming circuit includes one or more inputs and a complementary metal-oxide semiconductor (CMOS) circuit coupled to the programmable device. This design allows for writing and erasing of the programmable cell using a low and a high voltage input. Depending on the state that should be programmed into the PMC cell, a high voltage is applied to the anode and a low voltage is applied to the cathode or, reversely, a low voltage is applied to the anode and a high voltage is applied to the cathode of the PMC cell. However, voltage crosstalk might occur between the high voltage level of a selected bit line, used for programming a selected PMC cell, and a non-selected (or floating) neighboring bit line that could cause a programming failure. Therefore, there is a need for a method and a memory circuit that allow writing data in a memory cell of a CBRAM with reduced sensitivity to voltage crosstalk between bit lines during the programming operation.